1. Field of the Invention
The present invention relates to layout patterns of semiconductor integrated circuit devices. More specifically, it relates to layout patterns of semiconductor integrated circuit devices constituted such that layouts of functional circuit groups spread in one direction on a chip.
2. Description of Related Art
Conventionally, as one of the manners to meet the needs of higher integration of die size in semiconductor integrated circuit devices, there has been used a layout manner such that arrange functional circuits in a direction along with flow of signals to make up functional circuit groups wherein the functional circuits are constituted by CMOS units composed of pairs of PMOS transistors and NMOS transistors, and a plurality of logic circuits are included therein. This layout manner is applied to semiconductor memory devices such as dynamic random access memory excluding gate array type and standard cell type, i.e., so-called customized products.
It should be noted that CMOS unit or unit mentioned hereinafter indicates some types of unit structured with a pair of one or more PMOS transistors and one or more NMOS transistors, wherein the number of PMOS transistor(s) and that of NMOS transistor(s) are appropriately combined case by case. That is, circuit units that constitute fundamental functions of logic gate, transfer gate, and the like correspond to CMOS unit or unit. Furthermore, a single PMOS transistor or a single NMOS transistor can be classified into a type of unit herein as long as it is used as a capacitance element or a resistance element that has fundamental circuit function. Some elements not constituted by a PMOS transistor or an NMOS transistor are not always classified into unit. For example, a wiring layer switch for trimming, described later, cannot be a unit. This wiring layer switch determines connection between elements to constitute a fundamental circuit element. A group of elements connected by the wiring layer switch constitutes a fundamental circuit element and this corresponds to a unit. Accordingly, each element of the group is not defined as a unit. Furthermore, a capacitance element, a resistance element or the like are not classified into unit, either. This is because elements themselves can be buried in a wiring region and do not influence on element characteristics, layout efficiency or the like.
Layout manners of the gate array type and standard cell type are such that wirings are applied crosswise along a predetermined wiring grid pitch in a certain plot spreading two-dimensionally on a chip. Such layout aims to shorten connection processing time. On the other hand, the layout manner to arrange functional circuit groups in a direction along flow of signals aims to layout circuits with as high integration as possible on a restricted region making full use of restricted wiring layers.
FIG. 18 shows an example of chip layout for a semiconductor integrated circuit device to which three-metal layered processing is applied. A chip for the semiconductor integrated circuit device includes two memory cell regions M1 and M2 spreading in Y-direction. Between the memory cell regions M1 and M2, there are arranged functional circuit groups FNBL1, FNBL2 through FNBLn spreading in X-direction taking layout width BW1, BW2 through BWn, respectively in Y-direction. There are wired a power voltage wiring VCC extending from a power voltage pad VCP and a reference voltage wiring VSS from a reference voltage pad VSP across the functional circuit groups FNBL1, FNBL2 through FNBLn to supply power voltage VCC and reference voltage VSS to the functional circuit groups. Both the power voltage wiring VCC and the reference voltage wiring VSS are wired with a third metal layer M3L, a top layer. For higher circuit integration, each of the functional circuit groups FNBL1, FNBL2 through FNBLn is laid-out taking each of their layout widths at minimum.
FIG. 19 is an enlarged diagram of a portion 100 (shown in FIG. 18) directed to the functional circuit group FNBL1. The portion 100 of the functional circuit group FNBL1 consists of logic circuits CIR110, CIR120, CIR130, and CIR140. Each of the logic circuits CIR110, CIR120, CIR130, and CIR140 constitutes a CMOS unit. For example, in the CIR110, PMOS transistors P1, P2, P3 and NMOS transistors N1, N2, N3 are paired, respectively, to constitute three CMOS units. Connection wirings LV100 connect P-type and N-type MOS transistors. First metal layer M1L, bottom metal wiring layer, is used for the connection wirings LV100. As examples of CMOS units, here are shown an inverter gate, a transfer gate, and the like wherein a PMOS transistor and an NMOS transistor are connected one to one. However, types of CMOS unit are not limited to the above. Various logic gates such as NAND gate, NOR gate, MOS capacitor or the like, and fundamental circuit elements also are constituted with CMOS units. Furthermore, on a layer above of the PMOS transistors, there is wired a power voltage wiring VCC100 for supplying power voltage VCC to the functional circuit group FNBL1 with second metal layer M2L. The power voltage wiring VCC100 and a power voltage VCC wired with third metal layer M3L are connected by VIA contacts CVV at their crossing portion. Similarly, on a layer above of the NMOS transistors, there is wired a reference voltage wiring VSS100 for supplying reference voltage VSS to the functional circuit group FNBL1 with second metal layer M2L. The reference voltage wiring VSS100 and a reference voltage VSS wired with third metal layer M3L (not shown) are connected by VIA contacts at their crossing portion. Furthermore, between the power voltage wiring VCC100 and the reference voltage wiring VSS100 both wired with second metal layer M2L, there are wired internal wirings LH100 in accordance with necessity. In the internal wirings LH100, there are wired: input/output wirings for the functional circuit group FNBL1; internal wirings LH100 for connecting between pairs of PMOS-NMOS for CMOS units or between logic circuits CIR110 through CIR140; and the like. A block width BW1 for the functional circuit group FNBL1 is determined by the following three factors: (1) a width of the power voltage wiring VCC100 in response to current capacity required for the functional circuit group FNBL1; (2) a width of the reference voltage wiring VSS100; and (3) the number of the internal wirings LH100 determined by circuit structure and layout of the functional circuit group FNBL1. Block widths FNBL2 through FNBLn are determined by the same factors as the above.
In the forgoing, as metal layers, there have been mentioned first metal layer M1L, second metal layer M2L, and third metal layer M3L. In addition to them, there is poly-silicon (referred to as PolySi, hereinafter) layer as gate electrodes of the MOS transistors. That is, it is a four-layered wiring structure. There can be conceived of various processes to realize this four-layered wiring structure. FIG. 20 shows examples of possible processes. With process A, direct connections between adjacent layers are possible. That is, a VIA contact Cvv connects third metal layer M3L and second metal layer M2L, a VIA contact Cv connects the second metal layer M2L and first metal layer M1L, and a contact Cp connects the first metal layer M1L and PolySi layer. On the contrary, with process B, ohmic contact between PolySi layer and first metal layer M1L is impossible. Accordingly, it is required that a contact Cpp should connect the PolySi layer and second metal layer M2L. Accordingly, designers must design layouts of functional circuit groups FNBL1 through FNBLn taking process factors such as the above into consideration.
FIG. 21 and FIG. 22 show structural differences of internal wirings LH100 derived from differences of manufacturing processes. FIG. 21 shows a layout diagram in case the process A is applied thereto whereas FIG. 22 shows a case that the process B is applied thereto. The both cases share common structural factors as follows: (1) a power voltage wiring VCC 100 is wired with second metal layer M2L and PMOS transistors are arranged immediately below of the power voltage wiring VCC; (2) a reference voltage wiring VSS100 is wired with the second metal layer M2L and NMOS transistors are arranged immediately below the reference voltage wiring VSS100; (3) the PMOS transistors and the NMOS transistors are connected with first metal layer M1L one to one, thereby to constitute CMOS units; and (4) the first metal layer M1L and the second metal layer M2L are wired crosswise. In FIG. 21, there is no need to use second metal layer M2L so as to connect PolySi layer and first metal layer M1L because the contact Cp can connect the PolySi layer and the first metal layer M1L directly. Accordingly, a wiring region width of an internal wiring LH100 is determined by an internal wiring region IL100 on which CMOS units are arranged in a row and an input/output wiring region IOL100 that constitutes three lines on which logic circuits or the like are arranged. On the other hand, in FIG. 22, the case of the process B, PolySi layer and first metal layer M1L cannot be connected to each other directly. Therefore, contacts Cpp connect the PolySi layer and second layer so as to connect the PolySi layer and the first metal layer M1L indirectly. Accordingly, it is necessary to place the second metal layer M2L as an alternate route for connecting the first metal layer M1L and the PolySi layer indirectly. Therefore, a wiring region width of the internal wiring LH100 is determined by: an internal wiring region IL100 on which CMOS units are arranged in a row; another internal wiring region IL100 for the PolySi layer that constitutes two lines; and an input/output wiring region IOL100 that constitutes three lines on which logic circuits or the like are arranged.
FIG. 23 shows an example of a functional circuit. This functional circuit FNB comprises four logic circuits, namely, CIR1, CIR2, CIR3, and CIR4. The logic circuits CIR1 through CIR4 are composed of: capacitance factors NCn (n=1, 2, . . . ) constituted by NMOS transistors; capacitance factors PCn (n=1, 2, . . . ) constituted by PMOS transistors; wiring layer switches SW1, SW2 for trimming; N-type diffused resistance units RSn (n=1, 2, . . . ) and the like. In detail, the NMOS transistors are constituted by inverter gates In (n=1, 2, . . . ), NAND gates Dn (n=1, 2, . . . ), NOR gates Rn (n=1, 2, . . . ), complex gates ND, NR (complex of NAND logic and NOR logic), and transfer gates Tn (n=1, 2, . . . ).
FIG. 24 shows a layout pattern of functional circuit directed to FIG. 23 laid-out in accordance with the process B shown in FIG. 20 and FIG. 22. From the left side of the layout pattern, there are arranged logic circuits CIR1, CIR2, CIR3, and CIR4, in order. Enlarged layout patterns of respective four logic circuits are shown in FIG. 25 through FIG. 28.
The layout pattern of FIG. 24 is structured such that PMOS transistors are arranged within a N-type well region NW100 and a region other than the N-type well region NW100 is taken as a P-type well region PW100 on which NMOS transistors are arranged facing to the PMOS transistors. On the PMOS transistors, there is wired a power voltage wiring VCC100 composed of second metal layer M2L thereby to supply power voltage VCC to the PMOS transistors. In a similar manner, on the NMOS transistors, there is wired a reference voltage wiring VSS100 composed of second metal layer M2L thereby to supply reference voltage VSS to the NMOS transistors. Between the power voltage wiring VCC100 and the reference voltage wiring VSS100, there are arranged two internal wiring regions IL100 for connecting internal wirings used for the logic circuits CIR1 through CIR4 and for internal connection wiring used in the functional circuits FNB. Between the two internal wiring regions IL100 there is further arranged an input/output wiring region IOL100 for supplying input/output wiring to the external of the functional circuit FNB.
Furthermore, as shown in FIG. 25 through FIG. 28, the N-type well region NW100 is biased with the power voltage VCC. The power voltage wiring VCC100 constituted by second metal layer M2L is connected to the N-type well region with the contacts Cd101 indirectly, i.e., via first metal layer M1L through contacts Cv101. Furthermore, the P-type well region PW100 is biased with the reference voltage VSS. The reference voltage wiring VSS100 constituted by second metal layer M2L is connected to the P-type well region with the contacts Cd101 indirectly, i.e., via first metal layer M1L through contacts Cv101.
The PMOS transistor consists of a source region and a drain region. More specifically, P-type diffused layer PSD100 constituting the PMOS transistor is divided into the source region and the drain region by gate electrodes constituted by PolySi layer. Power voltage VCC is supplied to the source region as follows. Firstly, power voltage VCC coming out from the power voltage wiring VCC100 constituted by second metal layer M2L is transmitted to first metal layer M1L via the contacts Cv101 and then, further transmitted to the source region via the contacts Cd102. Similar to the PMOS transistor, the NMOS transistor consists of a source region and a drain region. More specifically, N-type diffused layer NSD100 constituting the NMOS transistor is divided into the source region and the drain region by gate electrodes constituted by PolySi layer. Reference voltage VSS is supplied to the source region as follows. Firstly, reference voltage VSS coming out from the reference voltage wiring VSS100 constituted by second metal layer M2L is transmitted to first metal layer M1L via the contacts Cv101 and then, further transmitted to the source region via the contacts Cd102. The drain region of the PMOS transistor and that of the NMOS transistor are connected via the first metal layer M1L and the contacts Cd103.
Out of the logic circuits CIR1 through CIR4 constituting the functional circuit FNB directed to FIG. 23, typical parts depicted in the layout pattern diagram of these logic circuits will be described by referring to FIGS. 25 through 28.
Firstly, the circuit structures of the CMOS units D1 through 14 for the logic circuit CIR1 will be described by referring to FIG. 25, the layout pattern of it. There are wired input wirings A, B, and C constituted by first metal layer M1L crosswise with second metal layer M2L, like running through rows of PMOS/NMOS transistors. The input wirings A, B, and C are laid out such that data can be inputted to the input wirings from whichever of the PMOS/NMOS transistors for the function circuit FNB. These input wirings A, B, and C are connected to the second metal layer M2L via the contacts Cv102 and from there is further connected to each gate terminal of the NAND gate D1 as a CMOS unit via contacts Cpp101. Drain terminals of the PMOS transistors and those of the NMOS transistors, constituting the NAND gate D1, are made conductive to each other by connecting the drain terminals to the first metal layer M1L via the contacts Cd103. Source terminals of respective transistors are connected to the power voltage wiring VCC100 or the reference voltage wiring VSS100 both of which are constituted by the second metal layer M2L in directly, i.e., by way of the contacts Cd102, the first metal layer M1L and the contacts Cv101, similar to connection for the well regions PW and NW.
An output wiring of the NAND gate D1 is drawn from the first metal layer M1L connected to the second metal layer M2L via contacts CV103, and finally connected to a gate terminal, namely, an input terminal of the inverter gate I1, via the contacts CPP102. Source terminals of respective transistors for the inverter gate I1 are connected in the same manner as the NAND gate D1. Similar to the NAND gate D1, a drain terminal is connected to other one via contacts Cd104 and the first metal wire M1L, thereby to constitute an output wiring. Subsequent inverter gates I2 through I4 are connected in the same manner as the inverter gate I1. An output wiring of the inverter gate I4 corresponds to an output wiring OUT1 for the functional circuit FNB. Accordingly, an output from the inverter gate I4 is transmitted to the second metal layer M2L in the input/output wiring region IOL100 from the first metal layer M1L via the contacts Cv104 and finally delivered to the external of the functional circuit FNB. Since other logic circuits for CMOS units such as NOR gate and complex logic are connected with the same wiring structure, therefore descriptions of the other logic circuits will be omitted.
Next, a switch unit SW1, a CMOS unit of the logic circuit CIR2, will be described by referring to FIG. 26, the layout pattern of it. The switch unit SW1 is structured such that the switch unit SW1 can decide connection/disconnection between the ends a-b by switching wiring layer masks. This structure is used in case circuit structure and circuit parameter are changed depending on form. Details of the structure will be described by referring the layout pattern of FIG. 26. The connection between the ends a and b has been connected with a certain wiring layer number that is different from its original wiring layer number at the time of layout design. When a wiring layer mask is formed, connection condition on the mask is switched, which depends on whether data with the different wiring layer number is synthesized or not. In FIG. 26, the connection between the ends a and b is conducted on the second metal layer M2L.
Further on, a capacitance unit CP1 as a CMOS unit of the logic circuit CIR3 and a diffused resistance unit RS1 will be described by referring to FIG. 27, the layout pattern of it. The capacitance unit CP1 comprises: capacitance factors PC1 through PC3 constituted by PMOS transistors; capacitance factors NC1 through NC3 constituted by NMOS transistors; and a switch unit SW2 for trimming. These portions will be described by referring to the layout pattern of FIG. 27. In the PMOS capacitance factor PC1, source/drain terminals of the PMOS transistors are connected to the power voltage wiring VCC100, thereby to constitute MOS capacitor between their gate terminals. Similar to the PMOS capacitance factor PC1, in the NMOS capacitance factor NC1, source/drain terminals of the NMOS transistors are connected to the reference voltage wiring VSS100, thereby to constitute MOS capacitor between their gate terminals. For gate terminals of each transistor, the switch unit SW2 for trimming is designed to switch area of gate terminal that contributes as capacitor.
Furthermore, in FIG. 27, the diffused resistance unit RS1 is constituted by using N-type diffused layer. The diffused resistance unit RS1 has a curved shape curving between a connection point c with an output wiring of the inverter gate I12 and a connection point d with the capacitance unit CP2.
There are seven output wirings OUT1 through OUT7 in the functional circuit FNB. As apparent from FIG. 24 through FIG. 28, a wiring region of the input/output wiring region IOL100 is determined a wired area constituted with the second metal layer M2L that is a center area sandwiched by rows of PMOS transistors immediately below the power voltage wiring VCC100 and rows of NMOS transistors immediately below the reference voltage wiring VSS100 in the layout patterns. On both sides of the wiring area, there are wired connection wirings in the functional circuit FNB, thereby to constitute an internal wiring regions IL100. Furthermore, widths of the power voltage wiring VCC100 and the reference voltage VSS100 are determined by power capacity required for circuit structuring of the functional circuit FNB. Along with that, widths of respective various wirings in a layout pattern of the functional circuit FNB are secondarily determined by: width of the input/output wiring region IOL100; that of internal wiring regions IL100, that of the power voltage wiring VCC100; that of the reference voltage wiring VSS100; or wiring width. More specifically, layout width is determined by a maximum area portion of the internal wiring region IL100 that differ depending on position to be laid-out. In this example, there are connected the most number of the internal wirings at the portion occupied by R2 through R5 of the logic circuits CIR2 whereby wiring width is determined. Accordingly, the layout patterns of the functional circuit FNB need to take wiring region width of the internal wiring LH100 so that wiring of the logic circuit CIR2 can be done. Wiring width is not necessary for the other logic circuits CIR1, CIR3, and CIR4. However, in order to arrange the logic circuits CIR1 through CIR4, wiring position of the power voltage wiring VCC100 and that of the reference voltage wiring VSS 100 must coincide with each other. Especially, even for the logic circuits CIR1, CIR3, and CIR4 that do not require width for internal wiring, a maximum width required for the logic circuit CIR2 must be secured.
As described in the above, in the layout patterns of the functional circuit FNB, the internal wiring region IL100 must be taken such that internal connection wiring can be laid-out at a region where the number of connection wirings to be connected among the logic circuits CIR1 through CIR4 is maximized. Accordingly, even if the number of internal wirings is a few at a portion other than the region where the number of internal wirings is a maxim, the above-mentioned internal wiring regions IL100 are secured. Portions remaining even after necessary internal wirings are wired are left as blanks. Taking destination of semiconductor integrated circuit device developments into consideration, it is clear that higher functions and lager scale design will be required for functional circuits FNB and along with that, the number of internal connection wirings will increase. Furthermore, as larger scale and more complicated circuit structure are endeavored, the number of connection stages of functional circuit groups, arranged with multi-stage structure in layout patterning, becomes larger. Therefore, there will be arranged the significant number of various logic circuits on a row of functional circuit group. As a result, there will co-exit logic circuits that need large number of internal connection wirings and those that need a few number of internal connection wirings. Therefore, large scale of internal wiring region IL100 must be taken for logic circuits of larger number of internal connection wirings whereas large scale of non-wiring region must be taken within the internal wiring region IL100. Due to this, in layout patterning of functional circuit group, it is hard to enhance layout efficiency of the region between the power voltage wiring VCC100 and the reference voltage wiring VSS100, which prevents higher integration design of semiconductor integrated circuit devices.
What is more, as higher function and larger scale design of functional circuit is achieved and layout pattern to arrange functional circuits in a row with multi-staged structure becomes popular, there will be accompanied with regions that need large number of internal connection wiring in the layout pattern. As a result, the number input/output wirings to the functional circuit group will increase, as well. Therefore, it is necessary to set wide widths for the internal wiring region IL100 and input/output wiring region IOL100. As a result, the distance between a PMOS transistor and an NMOS transistor facing to each other over the internal wiring region IL100 and the input/output wiring region IOL100 becomes longer and parasitic resistance of connection wirings and parasitic element component of parasitic capacity become larger. That is, since the PMOS transistors and the NMOS transistors are connected to each other to constitute a CMOS unit for a logic circuit, such parasitic element component is added thereto. As a result, signal waveform has a delay and the like that deteriorates characteristics of the signal waveform. More specifically, there is aroused a problem such that operation time difference occurs between the PMOS transistor and the NMOS transistor whereby through current occurs when transistors are switched.
Furthermore, as widths of the internal wiring region IL100 and the input/output wiring region IOL100 are wider, area for N-type well region NW100 and that for P-type well region PW100 are larger. It should be noted that, in a layout patterning, usage frequency of contact Cd101 and the like for applying voltage bias to the both types of well regions does not increase in proportion to increase of the wiring region. Contrarily, as the number of internal connection wirings and input/output wirings increases, it becomes difficult to secure arrangement regions of the contact Cd101 and the like, whereby usage frequency of the contact Cd101 and the like decreases in inverse proportion to the increase of the wirings. Therefore, there occurs a fear that the well regions NW100 and PW 100 cannot be biased and their well potentials become unstable. This may possibly cause the functional circuit groups to degrade latch-up resistance and to fluctuate characteristics due to fluctuation of back-bias effect in the PMOS/NMOS transistors, which is obstacle for stable operation of semiconductor integrated circuit devices.
When starting layout design, a designer considers wiring connections regarding logic circuits and arrangement order on the layout. Furthermore, considering arrangement order of functional circuit groups, the designer assumes the number of internal connection wirings and input/output wirings and staging manner of the wirings. Based on the above layout factors, the designer estimates a space between the power voltage wiring VCC100 and the reference voltage wiring VSS100 and starts wiring layout of power voltage VCC and reference voltage VSS on a chip. However, it is difficult to accurately estimate spacing at the initial stage of layout design and calculate spaces for the internal wiring region IL100 and the input/output wiring region IOL100. Especially in case progress of higher function and larger scale is achieved for functional circuits, accurate estimation of spacing may be impossible, which is problematic.
There may be a case such that, due to change of circuit design, internal connection wiring and input/output wiring and the like need to be added on the layout after wiring manners of the power voltage VCC and the reference voltage VSS are determined. In this case, the designer need to reconsider the number of the internal connection wirings and input/output wirings and staging manner of the wirings and estimate the space between the power voltage wiring VCC100 and the reference voltage wiring VSS100 again so as to secure a wiring region for the newly added wirings. On design work of semiconductor integrated circuit device field wherein speed-up of design span is required, there may be a case that layout design and circuit design are conducted in parallel and redesign of layout due to change of circuit design makes development time long.
Furthermore, in manufacturing process of semiconductor integrated circuit, there may be a case that wiring structure or the like of multi-layered wiring must be changed due to factors such as modification of device characteristics and change of manufacturing condition. For example, there may be changes of connection relationship, which depends on a factor whether or not ohmic contact to PolySi layer, shown in FIG. 20 through FIG. 22, is possible. In this case, a semiconductor integrated circuit device released with process A must be realized with process B. In process A, the first metal layer M1L and PolySi layer are connected to each other directly whereas in process B, the first metal layer M1L and PolySi layer are connected indirectly, i.e., via the second metal layer M2L. Therefore, in process B, it is necessary to secure a region for wiring the second metal layer M2L. In case making-up a layout library of process B from that of process A, it is necessary to change wirings of the power voltage VCC and the reference voltage VSS, which takes a long time to make-up a new layout library.
The present invention, attempted to resolve the above-noted problems with the prior art, relates to layout patterns of a semiconductor integrated circuit device wherein there are arranged functional circuit groups in one direction on a chip so as to enhance layout efficiency and prevent deterioration of element characteristics.
In order to achieve the above-stated object, a semiconductor integrated circuit device according to first aspect of the invention comprises: a pair of a first power wiring and a second power wiring, the pair being arranged in one direction, wherein a first region between the first power wiring and the second power wiring; fundamental circuit units constituted by combining one or more PMOS transistors and one or more NMOS transistors, the fundamental circuit units being arranged along with the first power wiring and the second power wiring; logic circuit units constituted by a plurality of the fundamental circuit units; functional circuit units constituted by a plurality of the logic circuit units, the functional circuit units being arranged in a manner of multi-staged structure; wherein at least one part of the PMOS transistors and that of the NMOS transistors are arranged below the first power wiring and the second power wiring; and unit connection wirings to connect between the fundamental circuit units or to connect between the logic circuit units, of which terminals terminate at the functional circuit units are arranged on second regions that are other than the first region, in case the unit connection wirings are constituted by a layer that is same as a wiring layer that constitutes the first power wiring and the second power wiring or by wiring layers that are under the wiring layer of the first and second power wirings.
In the semiconductor integrated circuit device according to the one aspect of the present invention, there are appropriately arranged functional circuit units in a manner of multi-staged structure along with a pair of the first power wiring and the second power wiring that form the first region between there. PMOS transistors and NMOS transistors constitute functional circuit units and at least one part of the PMOS transistor and that of the NMOS transistor are arranged below the first power wiring and the second power wiring. Connection wirings to be wired between the fundamental circuit units wired in the functional circuit units or between the logic circuit units are arranged on the second regions that are other than the first region. More specifically, the connection wirings are constituted by a layer the same as the wiring layer constituting the first and second power wirings or by layers under the wiring layer of the first and second power wirings
Therefore, no unit connection wirings are arranged on the first region. Accordingly, a wiring layout pattern does not leave any empty portions caused by connection between the fundamental circuit units. Furthermore, the first region can be used as an input/output wiring region wired running through the functional circuit units. Accordingly, layout efficiency of the first region can be thus enhanced and higher integration design of semiconductor integrated circuit device can be realized.
The above and the further objects and novel features of the invention will more fully appear from following detailed description when the same is read in connection with the accompanying drawings. It is to expressly understood, however, that the drawings are for the purpose of illustration only and are not intended as a definition of the limits of the invention.